Espressif Systems /ESP32 /TIMG0 /WDTCONFIG0

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Interpret as WDTCONFIG0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WDT_FLASHBOOT_MOD_EN)WDT_FLASHBOOT_MOD_EN 0 (NS100)WDT_SYS_RESET_LENGTH 0 (NS100)WDT_CPU_RESET_LENGTH 0 (WDT_LEVEL_INT_EN)WDT_LEVEL_INT_EN 0 (WDT_EDGE_INT_EN)WDT_EDGE_INT_EN 0 (OFF)WDT_STG3 0WDT_STG2 0WDT_STG1 0WDT_STG0 0 (WDT_EN)WDT_EN

WDT_STG3=OFF, WDT_CPU_RESET_LENGTH=NS100, WDT_SYS_RESET_LENGTH=NS100

Fields

WDT_FLASHBOOT_MOD_EN

When set flash boot protection is enabled

WDT_SYS_RESET_LENGTH

length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us

0 (NS100): 100ns

1 (NS200): 200ns

2 (NS300): 300ns

3 (NS400): 400ns

4 (NS500): 500ns

5 (NS800): 800ns

6 (NS1600): 1.6us

7 (NS3200): 3.2us

WDT_CPU_RESET_LENGTH

length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us

0 (NS100): 100ns

1 (NS200): 200ns

2 (NS300): 300ns

3 (NS400): 400ns

4 (NS500): 500ns

5 (NS800): 800ns

6 (NS1600): 1.6us

7 (NS3200): 3.2us

WDT_LEVEL_INT_EN

When set level type interrupt generation is enabled

WDT_EDGE_INT_EN

When set edge type interrupt generation is enabled

WDT_STG3

Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system

0 (OFF): Off

1 (INTERRUPT): Interrupt

2 (RESET): Reset CPU

3 (RESET_SYS): Reset system

WDT_STG2

Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system

WDT_STG1

Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system

WDT_STG0

Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system

WDT_EN

When set SWDT is enabled

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